New colours, new chips and waterproofing tipped for the iPhone 7 next week

It would be a surprise of unprecedented proportions if Apple didn't launch a brand new iPhone next Wednesday, and those charged with speculating about what's in store are having one last stab at some educated guesses this weekend.

KGI Securities analyst Ming-Chi Kuo, who has a respectable record at predicting Apple's next movements, has gone on record with a fresh batch of claims this weekend about the upcoming iPhone 7 - some of them we've heard before, and some of them are new.

Ming-Chi Kuo says the new iPhones will rock a new Apple A10 chip, which is apparently going to be substantially quicker than the A9 (and clocked at up to 2.4GHz). There are going to be two new colours, "dark black" and "piano black", while the classic silver grey look is going to be retired, he says.

Waterproofing, headphone jacks and more

We've previously heard rumours of waterproofing and the KGI Securities analyst is in agreement, predicting the iPhone 7 will have the same rating as the Apple Watch - specifically, being able to last for 30 minutes under 1 metre of water.

The headphone jack is indeed going away, Ming-Chi Kuo reckons, and he also agrees with many tipsters that a new dual-lens camera is coming to the larger 5.5-inch iPhone this year. That iPhone 7 Plus will have an extra gigabyte of RAM compared with the smaller model to help with the image processing (3GB vs 2GB).

16GB and 64GB storage options will be ditched, so your choice is going to be between 32GB, 128GB and 256GB, according to the analyst, and there are going to be numerous other minor upgrades too. In just a few days' time we're going to know for sure what Apple's been making - and we'll bring you the news as soon as it breaks.

Quanta Compute Plug—a computer the size and shape of an AC adapter

One of the biggest IT trade shows in Asia is going on right now in Taipei in Taiwan and one of the products being shown is grabbing a lot of attention—the Quanta Compute Plug—a complete computer that is the size and shape of an AC adapter. Initial reports suggest its main purpose is to convert a flat screen TV to a really "smart" TV.

Computers have been shrinking in size for many years, perhaps in reaction to the development of smartphones and tablet computers. Now, instead of taking up a desk, or serving as a portable device such as a laptop, computer makers are creating fully functional computers the size of thumb drives, or in this case, an AC adapter—complete with prongs. Of course it does not come with a hard drive, keyboard, mouse or screen, but some of those can be added because it does have two 3.0 USB ports and one HDMI port.

The Compute Plug was demonstrated at the show by Microsoft VP, Nick Parker while he was giving the keynote address. That was because the device runs Windows 10 (though which flavor is still not clear)—Parker showed how it can be used with Cortana and a Bluetooth headset allowing for hands free operation.

The idea behind such computers is apparently, to allow consumers to have multiple inexpensive computers in their home, each dedicated to certain specific tasks—tasks that typically cannot be done with a phone or tablet computer. The Compute Plug, for example, would allow for running full blown Word using a full sized keyboard, eliminating the need for lugging around a laptop, for students, or perhaps journalists. The downside to such a tiny computer, is of course, its low-power processor, hence its more dedicated use—not enough for massive gaming applications, but certainly enough to push 4K video to a screen. The Plug is not the first wall-plug computer, but it is the smallest thus far, and the first to run Windows.

Unfortunately, Parker did not give any specifics regarding when the little computer might be for sale, or how much it might cost. That presumably will come later from Quanta reps.

New chip design makes parallel programs run many times faster and requires one-tenth the code

Computer chips have stopped getting faster. For the past 10 years, chips' performance improvements have come from the addition of processing units known as cores.

In theory, a program on a 64-core machine would be 64 times as fast as it would be on a single-core machine. But it rarely works out that way. Most computer programs are sequential, and splitting them up so that chunks of them can run in parallel causes all kinds of complications.

In the May/June issue of the Institute of Electrical and Electronics Engineers' journal Micro, researchers from MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL) will present a new chip design they call Swarm, which should make parallel programs not only much more efficient but easier to write, too.

In simulations, the researchers compared Swarm versions of six common algorithms with the best existing parallel versions, which had been individually engineered by seasoned software developers. The Swarm versions were between three and 18 times as fast, but they generally required only one-tenth as much code—or even less. And in one case, Swarm achieved a 75-fold speedup on a program that computer scientists had so far failed to parallelize.

"Multicore systems are really hard to program," says Daniel Sanchez, an assistant professor in MIT's Department of Electrical Engineering and Computer Science, who led the project. "You have to explicitly divide the work that you're doing into tasks, and then you need to enforce some synchronization between tasks accessing shared data. What this architecture does, essentially, is to remove all sorts of explicit synchronization, to make parallel programming much easier. There's an especially hard set of applications that have resisted parallelization for many, many years, and those are the kinds of applications we've focused on in this paper."

Many of those applications involve the exploration of what computer scientists call graphs. A graph consists of nodes, typically depicted as circles, and edges, typically depicted as line segments connecting the nodes. Frequently, the edges have associated numbers called "weights," which might represent, say, the strength of correlations between data points in a data set, or the distances between cities.

Graphs crop up in a wide range of computer science problems, but their most intuitive use may be to describe geographic relationships. Indeed, one of the algorithms that the CSAIL researchers evaluated is the standard algorithm for finding the fastest driving route between two points.

Setting priorities

In principle, exploring graphs would seem to be something that could be parallelized: Different cores could analyze different regions of a graph or different paths through the graph at the same time. The problem is that with most graph-exploring algorithms, it gradually becomes clear that whole regions of the graph are irrelevant to the problem at hand. If, right off the bat, cores are tasked with exploring those regions, their exertions end up being fruitless.

Of course, fruitless analysis of irrelevant regions is a problem for sequential graph-exploring algorithms, too, not just parallel ones. So computer scientists have developed a host of application-specific techniques for prioritizing graph exploration. An algorithm might begin by exploring just those paths whose edges have the lowest weights, for instance, or it might look first at those nodes with the lowest number of edges.

What distinguishes Swarm from other multicore chips is that it has extra circuitry for handling that type of prioritization. It time-stamps tasks according to their priorities and begins working on the highest-priority tasks in parallel. Higher-priority tasks may engender their own lower-priority tasks, but Swarm slots those into its queue of tasks automatically.

Occasionally, tasks running in parallel may come into conflict. For instance, a task with a lower priority may write data to a particular memory location before a higher-priority task has read the same location. In those cases, Swarm automatically backs out the results of the lower-priority tasks. It thus maintains the synchronization between cores accessing the same data that programmers previously had to worry about themselves.

Indeed, from the programmer's perspective, using Swarm is pretty painless. When the programmer defines a function, he or she simply adds a line of code that loads the function into Swarm's queue of tasks. The programmer does have to specify the metric—such as edge weight or number of edges—that the program uses to prioritize tasks, but that would be necessary, anyway. Usually, adapting an existing sequential algorithm to Swarm requires the addition of only a few lines of code.

Keeping tabs

The hard work falls to the chip itself, which Sanchez designed in collaboration with Mark Jeffrey and Suvinay Subramanian, both MIT graduate students in electrical engineering and computer science; Cong Yan, who did her master's as a member of Sanchez's group and is now a PhD student at the University of Washington; and Joel Emer, a professor of the practice in MIT's Department of Electrical Engineering and Computer Science, and a senior distinguished research scientist at the chip manufacturer NVidia.

The Swarm chip has extra circuitry to store and manage its queue of tasks. It also has a circuit that records the memory addresses of all the data its cores are currently working on. That circuit implements something called a Bloom filter, which crams data into a fixed allotment of space and answers yes/no questions about its contents. If too many addresses are loaded into the filter, it will occasionally yield false positives—indicating "yes, I'm storing that address"—but it will never yield false negatives.

The Bloom filter is one of several circuits that help Swarm identify memory access conflicts. The researchers were able to show that time-stamping makes synchronization between cores easier to enforce. For instance, each data item is labeled with the time stamp of the last task that updated it, so tasks with later time-stamps know they can read that data without bothering to determine who else is using it.

Finally, all the cores occasionally report the time stamps of the highest-priority tasks they're still executing. If a core has finished tasks that have earlier time stamps than any of those reported by its fellows, it knows it can write its results to memory without courting any conflicts.

"I think their architecture has just the right aspects of past work on transactional memory and thread-level speculation," says Luis Ceze, an associate professor of computer science and engineering at the University of Washington. "'Transactional memory' refers to a mechanism to make sure that multiple processors working in parallel don't step on each other's toes. It guarantees that updates to shared memory locations occur in an orderly way. 

Thread-level speculation is a related technique that uses transactional-memory ideas for parallelization: Do it without being sure the task is parallel, and if it's not, undo and re-execute serially. Sanchez's architecture uses many good pieces of those ideas and technologies in a creative way."

Engineers develop the first on-chip RF circulator that doubles WiFi speeds with a single antenna

Last year, Columbia Engineering researchers were the first to invent a technology—full-duplex radio integrated circuits (ICs)—that can be implemented in nanoscale CMOS to enable simultaneous transmission and reception at the same frequency in a wireless radio. That system required two antennas, one for the transmitter and one for the receiver. And now the team, led by Electrical Engineering Associate Professor Harish Krishnaswamy, has developed a breakthrough technology that needs only one antenna, thus enabling an even smaller overall system. This is the first time researchers have integrated a non-reciprocal circulator and a full-duplex radio on a nanoscale silicon chip. The circulator research is published online April 15 in Nature Communications and the paper detailing the single-chip full-duplex radio with the circulator and additional echo cancellation was presented at the 2016 IEEE International Solid-State Circuits Conference on February 2.

"This technology could revolutionize the field of telecommunications," says Krishnaswamy, director of the Columbia High-Speed and Mm-wave IC (CoSMIC) Lab. "Our circulator is the first to be put on a silicon chip, and we get literally orders of magnitude better performance than prior work. Full-duplex communications, where the transmitter and the receiver operate at the same time and at the same frequency, has become a critical research area and now we've shown that WiFi capacity can be doubled on a nano scale silicon chip with a single antenna. This has enormous implications for devices like smartphones and tablets."

Krishnaswamy's group has been working on silicon radio chips for full duplex communications for several years and became particularly interested in the role of the circulator, a component that enables full-duplex communications where the transmitter and the receiver share the same antenna. In order to do this, the circulator has to "break" Lorentz Reciprocity, a fundamental physical characteristic of most electronic structures that requires electromagnetic waves travel in the same manner in forward and reverse directions.

"Reciprocal circuits and systems are quite restrictive because you can't control the signal freely," says PhD student Negar Reiskarimian, who developed the circulator and is lead author of the Nature Communications paper. "We wanted to create a simple and efficient way, using conventional materials, to break Lorentz Reciprocity and build a low-cost nanoscale circulator that would fit on a chip. This could open up the door to all kinds of exciting new applications."

The traditional way of breaking Lorentz Reciprocity and building radio-frequency circulators has been to use magnetic materials such as ferrites, which lose reciprocity when an external magnetic field is applied. But these materials are not compatible with silicon chip technology, and ferrite circulators are bulky and expensive. Krishnaswamy and his team were able to design a highly miniaturized circulator that uses switches to rotate the signal across a set of capacitors to emulate the non-reciprocal "twist" of the signal that is seen in ferrite materials. Aside from the circulator, they also built a prototype of their full-duplex system—a silicon IC that included both their circulator and an echo-cancelling receiver—and demonstrated its capability at the 2016 IEEE International Solid- State Circuits Conference this past February.

"Being able to put the circulator on the same chip as the rest of the radio has the potential to significantly reduce the size of the system, enhance its performance, and introduce new functionalities critical to full duplex," says PhD student Jin Zhou, who integrated the circulator with the full-duplex receiver that featured additional echo cancellation.

Non-reciprocal circuits and components have applications in many different scenarios, from radio-frequency full-duplex communications and radar to building isolators that prevent high-power transmitters from being damaged by back-reflections from the antenna. The ability to break reciprocity also opens up new possibilities in radio-frequency signal processing that are yet to be discovered. Full-duplex communications is of particular interest to researchers because of its potential to double network capacity, compared to half-duplex communications that current cell phones and WiFi radios use. The Krishnaswamy group is already working on further improving the performance of their circulator, and exploring "beyond-circulator" applications of non-reciprocity.

"What really excites me about this research is that we were able to make a contribution at a theoretically fundamental level, which led to the publication in Nature Communications, and also able to demonstrate a practical RF circulator integrated with a full-duplex receiver that exhibited a factor of nearly a billion in echo cancellation, making it the first practical full-duplex receiver chip and which led to the publication in the 2016 IEEE ISSCC," Krishnaswamy adds. "It is rare for a single piece of research, or even a research group, to bridge fundamental theoretical contributions with implementations of practical relevance. It is extremely rewarding to supervise graduate students who were able to do that!"

Self-folding robot walks, swims, climbs, dissolves

A demo sparking interest at the ICRA 2015 conference in Seattle was all about an origami robot that was worked on by researchers. More specifically, the team members are from the computer science and artificial intelligence lab at MIT and the department of informatics, Technische Universitat in Germany. "An untethered miniature origami robot that self-folds, walks, swims, and degrades" was the name of the paper, co-authored by Shuhei Miyashita. They focused on an origami robot that does just what the paper's title suggests. A video showing the robot in action showcases each move.

One can watch the robot walking on a trajectory, walking on human skin, delivering a block; swimming (the robot has a boat-shaped body so that it can float on water with roll and pitch stability); carrying a load (0.3 g robot); climbing a slope; and digging through a stack. It also shows how a polystyrene model robot dissolves in acetone.

Even Ackerman in IEEE Spectrum reported on the Seattle demo. Unfolded, the robot has a magnet and PVC sandwiched between laser-cut structural layers (polystyrene or paper). How it folds: when placed on a heating element, the PVC contracts, and where the structural layers have been cut, it creates folds, said Ackerman. The self-folding exercise takes place on a flat sheet; the robot folded itself in a few seconds. Kelsey Atherton in Popular Science, said, "Underneath it all, hidden like the Wizard of Oz behind his curtain, sit four electromagnetic coils, which turn on and off and makes the robot move forward in a direction set by its shape."

When placed in the tank of acetone, the robot dissolves, except for the magnet. The authors noted "minimal body materials" in their design enabled the robot to completely dissolve in a liquid environment, "a difficult challenge to accomplish if the robot had a more complex architecture."

Possible future directions: self-folding magnetic sensors into the body of the robot, which could lead to autonomous operation, and eventually, even inside the human body. The authors wrote, "Such autonomous '4D-printed' robots could be used at unreachable sites, including those encountered in both in vivo and bionic biological treatment."

Atherton said, for example, future designs based on this robot could be even smaller, and could work as medical devices sent under the skin.

Origami robots—reconfigurable robots that can fold themselves into arbitrary shapes—was discussed in an article last year in MIT News, quoting Ronald Fearing, a professor of electrical engineering and computer science at the University of California at Berkeley. 

Origami robotics, he said, is "a pretty powerful concept, because cutting planar things and folding is an inherently very low-cost process." He said, "Folding, I think, is a good way to get to the smaller robots."

New microchip demonstrates efficiency and scalable design

A new computer chip has been built by Princeton University researchers, which promises to boost performance of data centers that lie at the core of online services from email to social media.

Data centers - essentially giant warehouses packed with computer servers - enable cloud-based services, such as Gmail and Facebook, as well as store the staggeringly voluminous content available via the internet. Surprisingly, the computer chips at the hearts of the biggest servers that route and process information often differ little from the chips in smaller servers or everyday personal computers.

By designing their chip specifically for massive computing systems, the Princeton researchers say they can substantially increase processing speed while slashing energy needs. The chip architecture is scalable; designs can be built that go from a dozen processing units (called cores) to several thousand. Also, the architecture enables thousands of chips to be connected together into a single system containing millions of cores. Called Piton, after the metal spikes driven by rock climbers into mountainsides to aid in their ascent, it is designed to scale.

"With Piton, we really sat down and rethought computer architecture in order to build a chip specifically for data centers and the cloud," said David Wentzlaff, an assistant professor of electrical engineering and associated faculty in the Department of Computer Science at Princeton University. "The chip we've made is among the largest chips ever built in academia and it shows how servers could run far more efficiently and cheaply."

Other Princeton researchers involved in the project since its 2013 inception are Yaosheng Fu, Tri Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Matthew Matl, Xiaohua Liang, and Samuel Payne, who is now at NVIDIA. The Princeton team designed the Piton chip, which was manufactured for the research team by IBM. Primary funding for the project has come from the National Science Foundation, the Defense Advanced Research Projects Agency, and the Air Force Office of Scientific Research.

The current version of the Piton chip measures six by six millimeters. The chip has over 460 million transistors, each of which are as small as 32 nanometers - too small to be seen by anything but an electron microscope. The bulk of these transistors are contained in 25 cores, the independent processors that carry out the instructions in a computer program. Most personal computer chips have four or eight cores. In general, more cores mean faster processing times, so long as software ably exploits the hardware's available cores to run operations in parallel. Therefore, computer manufacturers have turned to multi-core chips to squeeze further gains out of conventional approaches to computer hardware.

In recent years companies and academic institutions have produced chips with many dozens of cores; but Wentzlaff said the readily scalable architecture of Piton can enable thousands of cores on a single chip with half a billion cores in the data center.

"What we have with Piton is really a prototype for future commercial server systems that could take advantage of a tremendous number of cores to speed up processing," said Wentzlaff.

The Piton chip's design focuses on exploiting commonality among programs running simultaneously on the same chip. One method to do this is called execution drafting. It works very much like the drafting in bicycle racing, when cyclists conserve energy behind a lead rider who cuts through the air, creating a slipstream.

At a data center, multiple users often run programs that rely on similar operations at the processor level. The Piton chip's cores can recognize these instances and execute identical instructions consecutively, so that they flow one after another, like a line of drafting cyclists. Doing so can increase energy efficiency by about 20 percent compared to a standard core, the researchers said.

A second innovation incorporated into the Piton chip parcels out when competing programs access computer memory that exists off of the chip. Called a memory traffic shaper, this function acts like a traffic cop at a busy intersection, considering each programs' needs and adjusting memory requests and waving them through appropriately so they do not clog the system. This approach can yield an 18 percent performance jump compared to conventional allocation.

The Piton chip also gains efficiency by its management of memory stored on the chip itself. This memory, known as the cache memory, is the fastest in the computer and used for frequently accessed information. In most designs, cache memory is shared across all of the chip's cores. But that strategy can backfire when multiple cores access and modify the cache memory. Piton sidesteps this problem by assigning areas of the cache and specific cores to dedicated applications. The researchers say the system can increase efficiency by 29 percent when applied to a 1,024-core architecture. They estimate that this savings would multiply as the system is deployed across millions of cores in a data center.

The researchers said these improvements could be implemented while keeping costs in line with current manufacturing standards. To hasten further developments leveraging and extending the Piton architecture, the Princeton researchers have made its design open source and thus available to the public.

"We're very pleased with all that we've achieved with Piton in an academic setting, where there are far fewer resources than at large, commercial chipmakers," said Wentzlaff. "We're also happy to give out our design to the world as open source, which has long been commonplace for software, but is almost never done for hardware."

Tomorrow's clothes may be made with light-emitting e-fabric

September 1, 2016 by Lisa Zyga

Researchers have fabricated a large-area textile that emits bright yellow light for more than 180 hours. The low-cost, flexible, transparent textile has potential applications in light-emitting clothing, signs, and architectural features.

The scientists have published a paper on the light-emitting textile in a recent issue of Flexible and Printed Electronics.

"Our work shows that ultra-flexible light emission on large areas can be realized on very lightweight textile electrodes," coauthor Thomas Lanz at Umeå University told Phys.org. "Traditionally, this was hard to come by, as these electrodes are typically quite rough. We have demonstrated that the light-emitting electrochemical cell's inherent fault tolerance is ideally suited for this type of transparent substrate. We see great potential for this technology in the field of wearables, as the device is highly conformal."

As the researchers explain, the key advantages of the new fabric are its high flexibility, light weight, and low cost. Currently, the most common transparent and flexible light-emitting device technology is the organic light-emitting diode (OLED), whose fabrication process involves expensive vacuum technology. In addition, the transparent electrodes in many OLEDs are made of indium-tin oxide (ITO), a relatively scarce material that is expensive to use on a large scale.

In contrast, the light-emitting textile presented in the new study is realized by spray-coating a light-emitting electrochemical cell (LEC) onto a transparent fabric-based electrode, resulting in a simpler and less expensive fabrication process compared to that used to make OLEDs. The fabric electrode consists of a weave of silver-coated copper wires and polymer fibers that are embedded in a polymer matrix, all of which is coated with a conductive ink.

Tests showed that the new textile emits highly uniform, bright yellow light for more than 180 hours, with the efficiency and luminescence both increasing over time. The researchers attribute these characteristics to the dynamic doping process that renders the LEC highly fault-tolerant.

In the future, the researchers plan to scale up the device to cover even larger emission areas and to make it semi-transparent, both of which look promising due to the flexible fabrication process.

Samsung offers new ePoP memory for smartphones

High-end smartphones to come, if they could talk, would deliver a message to Samsung, relaying thanks for the memory. Samsung Electronics has announced they are mass-producing an "embedded package on package" (ePoP) memory for use in high-end smartphones. Samsung said this is a tech improvement over existing two-package eMCP memory solutions. This presents an opportunity for more space for a battery pack in slim handsets. In talking about the ePoP phone memory stack, Korea IT Times described ePOP as "a memory chip package that combines DRAM, NAND flash and controller into one memory, enabling them to be piled on top of a mobile application processor."

The Samsung announcement was posted on the Samsung Electronics official global blog. The announcement said that this is a memory package with 3GB LPDDR3 DRAM, 32GB embedded multimedia card and a controller. The saved-space factor is key to the news; ePoP combines all essential memory components into a single package which can be stacked directly on top of the mobile processor without taking up any additional space—all memory on a single ePoP module. Samsung said ePoP does not need any space beyond the 225 square millimeters (15x15mm) taken up by the mobile application processor. Samsung also said the 3GB LPDDR3 mobile DRAM inside the ePoP operates at an I/O data transfer rate of 1,866Mb/s, with a 64-bit I/O bandwidth.

The one-package memory solution was created to address market needs for high speed, high energy efficiency and compactness. Jeeho Baek, senior vice president of memory marketing at Samsung Electronics, said Samsung expects to provide customers with "significant design benefits" along with faster, longer operations of multi-tasking features. Phone manufacturers can use the available space for components such as the battery pack. The new memory solution could save up to 40 percent of space in a smartphone.

The phone has special heat-resistant properties; Business Korea said, "As NAND flash is generally sensitive to heat, it was previously thought to be difficult to stack any above a mobile AP that processes at a high temperature. However, Samsung Electronics raised the heat resistance limit of its NAND flash, breaking the common idea in the industry, and launched ePoP, calling it 'wearable memory.'" Samsung has already been offering a similar single-package solution for wearable devices; the new configuration can be customized for flagship smartphones.

Going further into translation of how this might affect consumer phones, BGR's Chris Smith said on Thursday that people looking forward to seeing some of Samsung's 2015 "top-shelf devices in stores, including the Galaxy S6," might have reason to be excited about this new type of component. Since more space is cleared inside a mobile device, there is the opportunity of expanding the battery capacity of the device. "That's particularly useful for slimmer smartphones," said Smith, "as smartphone makers have yet to crack the battery problem and are still trying to figure out ways of improving smartphone battery life."

Will ePoP chips be a factor in Galaxy S6 phones? Even if not, Smith said that "such ePoP designs could be used in upcoming flagship smartphones and tablets, even if the Galaxy S6 is skipped."

New hacking technique imperceptibly changes memory virtual servers

Using a new attack technique, a team of Dutch hacking experts managed to alter the memory of virtual machines in the cloud without a software bug.

With this technique an attacker can crack the keys of secured virtual machines or install malware without being noticed. It's a new deduplication-based attack in which data can not only be viewed and leaked, but also modified using a hardware glitch. By doing so the attacker can order the server to install malicious and unwanted software or allow logins by unauthorized persons.

Deduplication and Rowhammer bug
With the new attack technique Flip Feng Shui (FSS), an attacker rents a virtual machine on the same host as the victim. This can be done by renting many virtual machines until one of them lands next to the victim. A virtual machine in the cloud is often used to run applications, test new software, or run a website. There are public (for everyone), community (for a select group) and private (for one organization accessible) clouds. The attacker writes a memory page that he knows exists in the victim on the vulnerable memory location and lets it deduplicate. As a result, the identical pages will be merged into one in order to save space (the information is, after all, the same). That page is stored in the same part of the memory of the physical computer. The attacker can now modify the information in the general memory of the computer. This can be done by triggering a hardware bug dubbed Rowhammer, which causes flip bits from 0 to 1 or vice versa, to seek out the vulnerable memory cells and change them.

Cracking OpenSSH
The researchers of the Vrije Universiteit Amsterdam, who worked together with a researcher from the Catholic University of Leuven, describe in their research two attacks on the operating systems Debian and Ubuntu. The first FFS attack gained access to the virtual machines through weakening OpenSSH public keys. The attacker did this by changing the victim's public key with one bit. In the second attack, the settings of the software management application apt were adjusted by making minor changes to the URL from where apt downloads software. The server could then install malware that presents itself as a software update. The integrity check could be circumvented by making a small change to the public key that verifies the integrity of the apt-get software packages.

Advise NSCS
Debian, Ubuntu, OpenSSH and other companies included in the research were notified before the publication and all have responded. The National Cyber Security Centre (NSCS) of the Dutch government has issued a fact sheet containing information and advice on FFS.

'Hack-Oscar'
The researchers presented their findings this week during the UNESIX Security Symposium 2016 in the United States. Recently they won the Oscar of hacking: the Pwnie for another attack technique that allows attackers to take over state-of-the-art software with all defences up, even if the software has no bugs.

New thin film transistor may open the door to the development of flexible electronic devices

The thin electronic devices could open the door to the development of flexible electronic devices with applications as wide-ranging as display technology to medical imaging and renewable energy production.

The team was exploring new uses for thin film transistors (TFT), which are most commonly found in low-power, low-frequency devices like the display screen you're reading from now. Efforts by researchers and the consumer electronics industry to improve the performance of the transistors have been slowed by the challenges of developing new materials or slowly improving existing ones for use in traditional thin film transistor architecture, known technically as the metal oxide semiconductor field effect transistor (MOSFET).

But the U of A electrical engineering team did a run-around on the problem. Instead of developing new materials, the researchers improved performance by designing a new transistor architecture that takes advantage of a bipolar action. In other words, instead of using one type of charge carrier, as most thin film transistors do, it uses electrons and the absence of electrons (referred to as "holes") to contribute to electrical output. Their first breakthrough was forming an 'inversion' hole layer in a 'wide-bandgap' semiconductor, which has been a great challenge in the solid-state electronics field.

Once this was achieved, "we were able to construct a unique combination of semiconductor and insulating layers that allowed us to inject "holes" at the MOS interface," said Gem Shoute, a PhD student in the Department of Electrical and Computer Engineering who is lead author on the article. Adding holes at the interface increased the chances of an electron "tunneling" across a dielectric barrier. Through this phenomenon, a type of quantum tunnelling, "we were finally able to achieve a transistor that behaves like a bipolar transistor."

"It's actually the best performing [TFT] device of its kind—ever," said materials engineering professor Ken Cadien, a co-author on the paper. "This kind of device is normally limited by the non-crystalline nature of the material that they are made of"

The dimension of the device itself can be scaled with ease in order to improve performance and keep up with the need of miniaturization, an advantage that modern TFTs lack. The transistor has power-handling capabilities at least 10 times greater than commercially produced thin film transistors.

Electrical engineering professor Doug Barlage, who is Shoute's PhD supervisor and one of the paper's lead authors, says his group was determined to try new approaches and break new ground. He says the team knew it could produce a high-power thin film transistor—it was just a matter of finding out how.

"Our goal was to make a thin film transistor with the highest power handling and switching speed possible. Not many people want to look into that, but the raw properties of the film indicated dramatic performance increase was within reach," he said. "The high quality sub 30 nanometre (a human hair is 50 micrometres wide) layers of materials produced by Professor Cadien's group enabled us to successfully try these difficult concepts"

In the end, the team took advantage of the very phenomena other researchers considered roadblocks.

"Usually tunnelling current is considered a bad thing in MOSFETs and it contributes to unnecessary loss of power, which manifests as heat," explained Shoute. "What we've done is build a transistor that considers tunnelling current a benefit."

The team has filed a provisional patent on the transistor. Shoute says the next step is to put the transistor to work "in a fully flexible medium and apply these devices to areas like biomedical imaging, or renewable energy."

There is a possibility that Smart chip makes low-powered, wireless neural implants

A small smart chip has been developed by Scientists at Nanyang Technological University, Singapore (NTU Singapore) that can be paired with neural implants for efficient wireless transmission of brain signals.

Neural implants when embedded in the brain can alleviate the debilitating symptoms of Parkinson's disease or give paraplegic people the ability to move their prosthetic limbs.

However, they need to be connected by wires to an external device outside the body. For a prosthetic patient, the neural implant is connected to a computer that decodes the brain signals so the artificial limb can move.

These external wires are not only cumbersome but the permanent openings which allow the wires into the brain increases the risk of infections.

The new chip by NTU scientists can allow the transmission of brain data wirelessly and with high accuracy.

Assistant Professor Arindam Basu from NTU's School of Electrical and Electronic Engineering said the research team have tested the chip on data recorded from animal models, which showed that it could decode the brain's signal to the hand and fingers with 95 per cent accuracy.

"What we have developed is a very versatile smart chip that can process data, analyse patterns and spot the difference," explained Prof Basu.

"It is about a hundred times more efficient than current processing chips on the market. It will lead to more compact medical wearable devices, such as portable ECG monitoring devices and neural implants, since we no longer need large batteries to power them."

Different from other wireless implants

To achieve high accuracy in decoding brain signals, implants require thousands of channels of raw data. To wirelessly transmit this large amount of data, more power is also needed which means either bigger batteries or more frequent recharging.

This is not feasible as there is limited space in the brain for implants while frequent recharging means the implants cannot be used for long-term recording of signals.

Current wireless implant prototypes thus suffer from a lack of accuracy as they lack the bandwidth to send out thousands of channels of raw data.

Instead of enlarging the power source to support the transmission of raw data, Asst Prof Basu tried to reduce the amount of data that needs to be transmitted.

Designed to be extremely power-efficient, NTU's patented smart chip will analyse and decode the thousands of signals from the neural implants in the brain, before compressing the results and sending it wirelessly to a small external receiver.

This invention and its findings were published last month in the prestigious journal, IEEE Transactions on Biomedical Circuits & Systems, by the Institute of Electrical and Electronics Engineers, the world's largest professional association for the advancement of technology.

Its underlying science was also featured in three international engineering conferences (two in Atlanta, USA and one in China) over the last three months.

Versatile smart chip with multiple uses

This new smart chip is designed to analyse data patterns and spot any abnormal or unusual patterns.

For example, in a remote video camera, the chip can be programmed to send a video back to the servers only when a specific type of car or something out of the ordinary is detected, such as an intruder.

This would be extremely beneficial for the Internet of Things (IOT), where every electrical and electronic device is connected to the Internet through a smart chip.

With a report by marketing research firm Gartner Inc predicting that 6.4 billion smart devices and appliances will be connected to the Internet by 2016, and will rise to 20.8 billion devices by 2020, reducing network traffic will be a priority for most companies.

Using NTU's new chip, the devices can process and analyse the data on site, before sending back important details in a compressed package, instead of sending the whole data stream. This will reduce data usage by over a thousand times.

Asst Prof Basu is now in talks with Singapore Technologies Electronics Limited to adapt his smart chip that can significantly reduce power consumption and the amount of data transmitted by battery-operated specialized sensors, such as video cameras.

The team is also looking to expand the applications of the chip into commercial products, such as to customise it for smart home sensor networks, in collaboration with a local electronics company.

The chip, measuring 5mm by 5mm can now be licensed by companies from NTU's commercialisation arm, NTUitive.

Samsung brings in world's first universal flash storage removable memory card line-up

Samsung Electronics today announced a piece of good news and unveiled the industry's first removable memory cards based on the JEDEC Universal Flash Storage (UFS) 1.0 Card Extension Standard, for use in high-resolution mobile shooting devices such as DSLRs, 3D VR cameras, action cams and drones. Coming in a wide range of storage capacities including 256, 128, 64 and 32 gigabyte (GB), Samsung's UFS cards are expected to bring a significant performance boost to the external memory storage market, allowing much more satisfying multimedia experiences.

"Our new 256GB UFS card will provide an ideal user experience for digitally-minded consumers and lead the industry in establishing the most competitive memory card solution," said Jung-bae Lee, senior vice president, Memory Product Planning & Application Engineering, Samsung Electronics "By launching our new high-capacity, high-performance UFS card line-up, we are changing the growth paradigm of the memory card market to prioritize performance and user convenience above all."

Samsung's new 256GB UFS removable memory card ─ simply referred to as the UFS card will provide greatly improved user experiences, especially in high-resolution 3D gaming and high-resolution movie playback. It provides more than five times faster sequential read performance compared to that of a typical microSD card, reading sequentially at 530 megabytes per second (MB/s) which is similar to the sequential read speed of the most widely used SATA SSDs. With this UFS card, consumers have the ability to read a 5GB, Full-HD movie in approximately 10 seconds, compared to a typical UHS-1 microSD card, which would take over 50 seconds with 95MB/s of sequential reading speed. Also, at a random read rate of 40,000 IOPS, the 256GB card delivers more than 20 times higher random read performance compared to a typical microSD, which offers approximately 1,800 IOPS.

When it comes to writing, the new 256GB UFS card processes 35,000 random IOPS, which is 350 times higher than the 100 IOPs of a typical microSD card, and attains a 170MB/s sequential write speed, almost doubling the top-end microSD card speed. With these substantial performance improvements, the new 256GB UFS card significantly reduces multimedia data downloading time, photo thumbnail loading time and buffer clearing time in burst shooting mode, which, collectively, can be particularly beneficial to DSLR camera users. To shoot 24 large/extra fine JPEG photographs (1,120 megabyte (MB)-equivalent) continuously with a high-end DSLR camera, the 256GB UFS card takes less than seven seconds, compared to a UHS-1 microSD card which typically takes about 32 seconds, at 35MB/s.

To achieve the highest performance and most power-efficient data transport, the UFS card supports multiple commands with command queuing features and enables simultaneous reading and writing through the use of separately dedicated paths, doubling throughput.

Samsung has been aggressive in preparing UFS solutions for the marketplace, while contributing to JEDEC standardization of the Universal Flash Storage 2.0 specification in September 2013 and the Universal Flash Storage (UFS) 1.0 Card Extension standard in March 2016. Following its introduction of the industry-first 128GB embedded UFS chip in January 2015, the company successfully launched a 256GB embedded UFS memory for high-end mobile devices in February of this year. As of earlier this month, Samsung also completed the Universal Flash Storage Association (UFSA)'s certification program that evaluates electrical and functional specifications for compatibility of a UFS card, and Samsung's new UFS card products were approved as UFSA-certified UFS cards with the right to use the official UFS logo for the first time in the industry.

A rechargeable battery to power a home from rooftop solar panels

Scientists have said that a rechargeable battery that could make storage of electricity from intermittent energy sources like solar and wind safe and cost-effective for both residential and commercial use. The new research builds on earlier work by members of the same team that could enable cheaper and more reliable electricity storage at the grid level.

The mismatch between the availability of intermittent wind or sunshine and the variability of demand is a great obstacle to getting a large fraction of our electricity from renewable sources. This problem could be solved by a cost-effective means of storing large amounts of electrical energy for delivery over the long periods when the wind isn't blowing and the sun isn't shining.

In the operation of the battery, electrons are picked up and released by compounds composed of inexpensive, earth-abundant elements (carbon, oxygen, nitrogen, hydrogen, iron and potassium) dissolved in water. The compounds are non-toxic, non-flammable, and widely available, making them safer and cheaper than other battery systems.

"This is chemistry I'd be happy to put in my basement," says Michael J. Aziz, Gene and Tracy Sykes Professor of Materials and Energy Technologies at Harvard Paulson School of Engineering and Applied Sciences (SEAS), and project Principal Investigator. "The non-toxicity and cheap, abundant materials placed in water solution mean that it's safe—it can't catch on fire—and that's huge when you're storing large amounts of electrical energy anywhere near people."

This new rechargeable battery chemistry was discovered by post-doctoral fellow Michael Marshak and graduate student Kaixiang Lin working together with co-lead author Roy Gordon, Thomas Dudley Cabot Professor of Chemistry and Professor of Materials Science at Harvard.

"We combined a common organic dye with an inexpensive food additive to increase our battery voltage by about 50 percent over our previous materials," says Gordon. The findings "deliver the first high-performance, non-flammable, non-toxic, non-corrosive, and low-cost chemicals for flow batteries."

Unlike solid-electrode batteries, flow batteries store energy in liquids contained in external tanks, similar to fuel cells. The tanks (which set the energy capacity), as well as the electrochemical conversion hardware through which the fluids are pumped (which sets peak power capacity), can be sized independently. Since the amount of energy that can be stored can be arbitrarily increased by scaling up only the size of the tanks, larger amounts of energy can be stored at lower cost than traditional battery systems.

The active components of electrolytes in most flow battery designs have been metal ions such as vanadium dissolved in acid. The metals can be expensive, corrosive, tricky to handle, and kinetically sluggish, leading to inefficiencies. Last year, Aziz and his Harvard colleagues demonstrated a flow battery that replaced metals with organic (carbon-based) molecules called quinones, which are abundant, naturally occurring chemicals that are integral to biological processes like photosynthesis and cellular respiration. While quinones in aqueous solution formed the negative electrolyte side of the battery, the positive side relied on a conventional bromine-bearing electrolyte that is used in several other batteries. The high performance and low cost of the technology, which Harvard has licensed to a company in Europe, hold the potential to provide scalable grid-level storage solutions to utilities.

But bromine's toxicity and volatility make it most suitable for settings where trained professionals can deal with it safely behind secure fences.

So the team began searching for a new recipe that would provide comparable storage advantages—inexpensive, long lasting, efficient—using chemicals that could be safely deployed in homes and businesses. Their new battery, described in a paper published today in the journal Science, replaces bromine with a non-toxic and non-corrosive ion called ferrocyanide.

"It sounds bad because it has the word 'cyanide' in it," explains co-lead author Marshak, who is now assistant professor of chemistry at the University of Colorado Boulder. "Cyanide kills you because it binds very tightly to iron in your body. In ferrocyanide, it's already bound to iron, so it's safe. In fact, ferrocyanide is commonly used as a food additive, and also as a fertilizer."

Because ferrocyanide is highly soluble and stable in alkaline rather than acidic solutions, the Harvard team paired it with a quinone compound that is soluble and stable under alkaline conditions, in contrast to the acidic environment of their original battery developed last year.

Marshak compares exposure to the concentrated alkaline solution to coming into contact with a damaged disposable AA battery. "It's not something you want to eat or splash around in, but outside of that it's really not a problem."

There are other advantages to using alkaline solution. Because it is non-corrosive, the flow battery system components can be constructed of simpler and much less expensive materials such as plastics.

"First generation flow batteries were single-element couples - transition metals like vanadium or iron or chrome," says Michael Perry, Project Leader for Electrochemical Systems at United Technologies Research Center, who was not involved in the work. "Now we're seeing the possibility of engineered molecules giving us the properties and attributes that we want in one complete system. More work is required and justified but the Harvard team is really demonstrating the promise of next-generation chemistries."

Robert F. Savinell, Distinguished University Professor and George S. Dively Professor of Engineering at Case Western Reserve University, another battery expert who was not part of the Harvard research, agrees that the new technology offers significant advantages over other flow batteries concepts, including "potential very low costs with sustainable materials, high efficiencies at practical power densities, and safe and simple operation." He adds: "It should be expected that this flow battery approach will have a short development and scale-up path for fast commercial introduction."

Harvard's Office of Technology Development has been working closely with the research team to navigate the shifting complexities of the energy storage market and build relationships with companies well positioned to commercialize the new chemistries.

The demand for battery storage is driven by regulatory factors as much as economic ones. In some states, as well as many parts of the world, if it can't be instantaneously used by meeting electricity demand, solar energy incident on solar panels goes to waste unless the electricity is stored. However, in many states, customers have the right to sell electricity produced by rooftop solar panels at high consumer rates under a regulatory scheme called net metering. Under those circumstances, consumers have little incentive to install batteries. But market experts like William W. Hogan, Raymond Plank Professor of Global Energy Policy at Harvard Kennedy School, believe that such policies are ultimately "uneconomic and unsustainable." And as more and more homeowners install solar panels, utilities are opposing requirements to buy electricity from their customers.

Hogan says net metering is one of a series of "regulatory gimmicks designed to make solar more attractive" and predicts that eventually consumers with rooftop photovoltaic panels will lose the option of exchanging electricity for discounts on their utility bills. When that happens, these homeowners have an incentive to invest in battery storage.

That's the emerging market opportunity that Tesla Motors entrepreneur Elon Musk hopes to leverage with his company's recently-announced Powerwall system. But the flow battery design engineered by Aziz and his Harvard colleagues offers potential advantages in cost and the length of time it can maintain peak discharge power compared to lithium batteries.

"This has potential because photovoltaics are growing so fast," Aziz says. "A cloud comes over your solar installation and BAM - the production goes crashing down. Then the cloud goes away and the production goes shooting up. The best way of dealing with that is with batteries."

A low-power always-on camera with gesture recognition has been developed recently

Smart devices that wake up with voice commands have gained popularity in recent years, and now researchers at Georgia Institute of Technology have taken it one step farther: an always-on camera.

Designed with a combination of low-power hardware and energy efficient image processing software, the always-on camera is capable of watching for specific types of movement without draining batteries or running up electricity bills.

"Right now cameras are very hard to run on passive power just because they burn so much power themselves," said Justin Romberg, a professor in Georgia Tech's School of Electrical and Computer Engineering. "This combination of efficient signal processing and a novel hardware design lowers the power requirement and means that some of these other options to power it might be open."

The research, which was highlighted at the International Symposium on Low Power Electronics and Design Aug. 8-10, was sponsored by Intel Corp. and the National Science Foundation.

While reducing the frame rate of a camera plays a role in lowering power demands, to achieve the power savings needed for this project, the researchers programmed the camera to track motion in a more generalized way that still preserved crucial details about what was being tracked. That requires much less power to process than tracking individual pixels throughout the entire field of view.

"What this camera is actually looking at is not pixel values, but pixels added together in all different ways and a dramatically smaller number of measurements than if you had it in a standard mode," Romberg said.

The always-on camera was primarily designed as a way to wake up devices. But its ability to recognize specific gestures expands the possibilities – such as a camera that wakes up with a specific pattern or movement almost like a secret handshake.

"We wanted to devise a camera that was capturing images all of the time, and then once you have a particular gesture – like you write a Z in the air – it's going to wake up," said Arijit Raychowdhury, an associate professor in the School of Electrical and Computer Engineering. "To make that work without affecting the battery life, we wanted it to be so low power that you can power it with harvested ambient energy, such as with a photovoltaic cell."

Programming a camera to recognize specific gestures and wake up only when needed is also a way of conserving total system energy, Raychowdhury said.

"Simple motion detection is a well-studied area of research, and there are commercial products that support motion detection," he said. "But the problem is that a camera that can just detect motion – and not specific patterns in motion or gestures – is going to wake up more often, even when it doesn't need to."

Such a low-power camera could be useful in a range of applications, especially for camera systems in remote locations where efficiency is crucial.

"If you have a camera in the field, you want them to use as little energy as possible and only record events when necessary," Romberg said.

Other applications include specialized surveillance, robotics and consumer electronics with hands-free operation, and the researchers are already working on adding wireless functionality to transmit images and data with an antenna.